The present invention describes an improvement in a frequency synthesizer specifically intended for use in a telecommunications application. Such frequency synthesizers must exhibit, among other things, low spurious spectral content, fast settling time of frequency or phase, and low sideband phase noise.
Many synthesizers are comprised of phase locked loops that use integer division methods to produce the desired ouput frequency. These phase-locked loops exhibit high division ratios, which causes difficulty in optimizing many of the above performance parameters.
A fractional-N type phase locked loop ("PLL") divides by a fractional value in order to lower the division ratio while maintaining the same frequency step size.
Briefly, this is accomplished as follows. A fractional counting scheme uses at least two different division ratios, that are dynamically switched with each reference cycle. For example, to divide by 133.125, division by 133 is controlled during seven cycles, and division by 134 during an eighth cycle. Hence, the average division ratio over eight reference cycles is 133.125. During the time that the system is dividing by 133, however, the instantaneous phase error seen by the phase detector accumulates with each reference cycle. Then, at the end of the eighth cycle, during which the system divides by 134, the error rapidly decreases to zero, only to begin accumulating again with the repeated process. The resultant sawtooth waveform modulates the synthesizer's output frequency in an FM fashion, causing an undesired spur in the output spectrum. Hence, this fractional counting scheme reduces the loop division ratio, but does so only at the expense of added spurs which are generated by the fractional counting scheme.
The fractional spur can be compensated by adding an equal amount of energy per compare cycle, opposite in phase to the sawtooth output of the phase detector. This removes the AC component, which cancels the effect of the fractional modulation producing the undesired spurs. However, the inventor of the present invention found that this cancellation is extremely temperature dependent. Even over a moderate temperature range, the amount of cancellation may vary significantly. The subject of this invention is an improved way to compensate this temperature-based variation.
Temperature compensation of phase locked loops and other frequency division structures is known, in general, in the art.
U.S. Pat. No. 4,397,537, for example, shows that a phase detector with differential outputs can be temperature compensated against common mode fluctuations via the common mode rejection ratio of an OP-Amp. It also teaches temperature-compensating the voltage controlled oscillator ("VCO") of the loop.
U.S. Pat. No. 4,929,918 shows a frequency locked loop ("FLL") can be used in conjunction with a PLL to dynamically compensate the VCO against component tolerance variations as well as temperature fluctuations.
U.S. Pat. Nos. 4,484,355; 5,126,699; 5,204,975; and 5,216,389 teach temperature compensation of crystal reference oscillators used as inputs to a PLL. U.S. Pat. Nos. 5,136,260; 5,061,907; and 4,519,086 teach temperature compensation of VCO's used in PLL's.
None of the these patents, however, teach or suggest a way in which temperature compensation could be extended to the spur cancellation of a fractional-N counting type phase locked loop.
More generally, all of these prior art documents teach that each element of a phase locked loop is separately compensated, using independent compensation network, respectively. The present invention, for the first time, teaches a way in which a single temperature compensation in one part of a loop can be used to temperature compensate a process in a different part of the loop.